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DESCRIPTION
The WM8711BL is an ultra-small, low power stereo DAC with an integrated headphone driver. It is designed specifically for portable audio systems requiring hi-fi stereo playback through headphones. Stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. Stereo audio outputs are buffered for driving headphones from a programmable volume control, line level outputs are also provided along with anti-thump mute and power up/down circuitry. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. The device is available in an ultrasmall 24-lead QFN (4x4x0.9 mm Body) package. A USB clocking mode is provided where all audio rates can be derived from a single 12MHz or 24MHz MCLK, saving on the need for a PLL or multiple crystals.
WM8711BL
Ultra-Small Audio DAC with Headphone Amplifier
FEATURES
* * Audio Performance - DAC SNR 97dB (`A' weighted) at AVDD = 3.3V - DAC SNR 90dB (`A' weighted) at AVDD = 1.8V Low Power Headphone Playback - Down to 6mW at 1.8V - 1.42 - 3.6V Digital Supply Operation - 1.8 - 3.6 V Analogue Supply Operation DAC Sampling Frequency: 8kHz - 96kHz 2 or 3-Wire MPU Serial Control Interface Programmable Audio Data Interface Modes 2 - I S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths - Master or Slave Clocking Mode Stereo Audio Outputs Output Volume and Mute Controls Highly Efficient Headphone Driver 24-lead QFN (4x4x0.9 mm) package
* * *
* * * *
APPLICATIONS
* * Multimedia Mobile Phones Portable MP3 / CD Players
BLOCK DIAGRAM
MODE SCLK SDIN CSB AGND AVDD VMID
W WM8711B
HPVDD CONTROL INTERFACE HPGND RLINEIN
MUTE VOL/ MUTE H/P DRIVER
RHPOUT
DACDAT DACLRC
DIGTAL AUDIO INTERFACE
DAC
+6 to -73dB 1 dB Steps
ROUT DIGITAL FILTERS LOUT DAC
+6 to -73dB 1 dB Steps VOL/ MUTE MUTE
OSC
CLKIN DIVIDER (Div x1, x2) CLKIN DIVIDER (Div x1, x2)
BCLK
H/P DRIVER
LHPOUT
LLINEIN
DCVDD (1.5V)
DBVDD (3.3V)
XTI/MCLK
WOLFSON MICROELECTRONICS plc
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CLKOUT
DGND
XTO
Production Data, April 2007, Rev 4.1
Copyright (c)2007 Wolfson Microelectronics plc
WM8711BL
Production Data
TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES ............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY .....................................................................................................7 POWER CONSUMPTION ......................................................................................8 HEADPHONE SNR VS AVDD ...............................................................................9 ANALOGUE SUPPLY CURRENT VS AVDD.........................................................9
DIGITAL AUDIO INTERFACE - MASTER MODE........................................................ 10 DIGITAL AUDIO INTERFACE - SLAVE MODE ........................................................... 11 MPU INTERFACE TIMING........................................................................................... 11
DEVICE DESCRIPTION .......................................................................................13
INTRODUCTION.......................................................................................................... 13 AUDIO SIGNAL PATH ................................................................................................. 14 DEVICE OPERATION.................................................................................................. 19 AUDIO DATA SAMPLING RATES ............................................................................... 27 ACTIVATING DSP AND DIGITAL AUDIO INTERFACE ............................................... 30 SOFTWARE CONTROL INTERFACE.......................................................................... 30 POWER DOWN MODES ............................................................................................. 32 REGISTER MAP .......................................................................................................... 34
DAC FILTER RESPONSES .................................................................................38 DIGITAL DE-EMPHASIS CHARACTERISTICS ..................................................40 RECOMMENDED EXTERNAL COMPONENTS ..................................................41 PACKAGE DIMENSIONS - QFN.........................................................................42 IMPORTANT NOTICE ..........................................................................................43
ADDRESS:................................................................................................................... 43
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WM8711BL
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE TEMPERATURE AVDD RANGE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE
WM8711BLGEFL/V
-25 to 85oC
1.8 to 3.6V
24-lead QFN (Pb-free) 24-lead QFN (Pb-free, tape and reel)
MSL3
260oC
WM8711BLGEFL/RV Note: Reel quantity = 3500
-25 to 85oC
1.8 to 3.6V
MSL3
260oC
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WM8711BL PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note: 1. 2. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB. NAME XTI/MCLK XTO DCVDD DGND DBVDD CLKOUT BCLK DACDAT DACLRC HPVDD LHPOUT RHPOUT HPGND LOUT ROUT AVDD AGND VMID RLINEIN LLINEIN MODE CSB SDIN SCLK TYPE Digital Input Digital Output Supply Ground Supply Digital Output Digital Input/Output Digital Input Digital Input/Output Supply Analogue Output Analogue Output Ground Analogue Output Analogue Output Supply Ground Analogue Output Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input Crystal Output Digital Core VDD Digital GND Digital Buffers VDD Buffered Clock Output Digital Audio Bit Clock, Pull Down (see Note 1) DAC Digital Audio Data Input DESCRIPTION Crystal Input or Master Clock Input (MCLK)
Production Data
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1) Headphone VDD Left Channel Headphone Output Right Channel Headphone Output Headphone GND Left Channel Line Output Right Channel Line Output Analogue VDD Analogue GND Mid-rail reference decoupling point Right Channel Line Input (AC coupled) Left Channel Line Input (AC coupled) Control Interface Selection, Pull up (see Note 1) 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active low, Pull up (see Note 1) 3-Wire MPU Data Input / 2-Wire MPU Data Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input
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WM8711BL
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Notes: 1. 2. 3. Analogue and digital grounds must always be within 0.3V of each other. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) DCVDD must always be less than or equal to DBVDD MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +3.63V +3.63V DVDD +0.3V AVDD +0.3V +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supply range Ground SYMBOL DCVDD DBVDD AVDD, HPVDD DGND,AGND,HPGND TEST CONDITIONS MIN 1.42 1.8 1.8 0 TYP MAX 3.6 3.6 3.6 UNIT V V V V
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WM8711BL
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Input LOW level Input HIGH level Output LOW Output HIGH Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off Hysteresis DCVDD Threshold Off -> On Analogue Reference Levels Reference voltage (VMID) Potential divider resistance 0dBFs Full scale output voltage Signal to Noise Ratio A-weighted (Note 1,2) SNR VVMID RVMID At LINE outputs AVDD=HPVDD=3.3V AVDD=HPVDD=1.8V AVDD=HPVDD=1.8V, fs = 96kHz Dynamic Range (Note 2) Total Harmonic Distortion DR THD A-weighted, -60dB full scale input AVDD=HPVDD=3.3V, 1kHz, 0dBFS AVDD=HPVDD=1.8V, 1kHz, 0dBFs AVDD=HPVDD=1.8V 1kHz, -3dBFs Power Supply Rejection Ratio PSRR 1kHz 100mVpp 20Hz to 20kHz 100mVpp DAC channel separation 0dB Full scale output voltage Signal to Noise Ratio A-weighted (Note 1,2) Total Harmonic Distortion SNR THD AVDD=HPVDD=3.3V AVDD=HPVDD=1.8V AVDD=HPVDD=3.3V, 1kHz, 0dBFS AVDD=HPVDD=1.8V , 1kHz, 0dB 90 1kHz, 0dB signal 85 85 AVDD/2 50k AVDD/3.3 97 90 90 90 -84 -81 -88 50 45 100 AVDD/3.3 99 101 -90 -93 -85 dB dB Vrms dB dB -75 dB dB V Vrms dB 0.9 0.3 0.6 V V V SYMBOL VIL VIH VOL VOH IOL = 1mA IOH = -1mA 0.9 x DBVDD 0.7 x DBVDD 0.1 x DBVDD TEST CONDITIONS MIN TYP MAX 0.3 x DBVDD UNIT V V V V
Digital Logic Levels (CMOS Levels)
Line Output for DAC Playback Only (Load = 10K. 50pF)
Analogue Line Input to Line Output (Load = 10k. 50pF, No Gain on Input ) Bypass Mode
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WM8711BL
Test Conditions AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Stereo Headphone Output 0dB Full scale output voltage Max Output Power PO AVDD=HPVDD=3.3V, RL = 32 AVDD=HPVDD=1.8V, RL = 32 AVDD=HPVDD=1.8V, RL = 16 Signal to Noise Ratio A-weighted (Note 1,2) Total Harmonic Distortion SNR THD AVDD=HPVDD=3.3V AVDD=HPVDD=1.8V AVDD=HPVDD=3.3V, 1kHz, RL = 32 @ PO = 14mW rms AVDD=HPVDD=1.8V, 1kHz, RL = 32 @ PO = 4.5mW rms Power Supply Rejection Ratio PSRR 1kHz 100mVpp 20Hz to 20kHz 100mVpp Programmable Gain Programmable Gain Step Size Mute attenuation 1kHz 1kHz 1kHz, 0dB -73 80 AVDD/3.3 20 9 18 96 86 0.07 -63 0.05 -66 50 45 6 1 80 6 dB dB dB 0.18 -55 dB % dB dB Vrms mW SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. 4. 5. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
2.
6.
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WM8711BL POWER CONSUMPTION
POWEROFF CLKOUTPD OSCPD OUTPD MODE DESCRIPTION DACPD CURRENT CONSUMPTION TYPICAL AVDD V 0 0 0 1.8 2.6 3.0 3.3 0 1 1 0 0 1.8 2.6 3.0 3.3 Standby No clocks 0 1 1 1 1 1.8 2.6 3.0 3.3 Power Down No clocks 1 1 1 1 1 1.8 2.6 3.0 3.3 Table 1 Current Consumption Examples Notes: 1. 2. 3. TA = +25oC, fs = 48kHz. All figures are quiescent, with no signal. The power dissipation in the headphone itself not included in the above table. I (mA) 1.8 2.7 3.1 3.4 1.8 2.6 3.1 3.4 9.8 15.4 16.5 17 HPVDD V 1.8 2.6 3.0 3.3 1.8 2.6 3.0 3.3 1.8 2.6 3.0 3.3 1.8 2.6 3.0 3.3 I (mA) 0.8 1.3 1.5 1.7 0.8 1.3 1.5 1.7 DCVDD V 1.5 2.6 3.0 3.3 1.5 2.6 3.0 3.3 1.5 2.6 3.0 3.3 1.5 2.6 3.0 3.3 I (mA) 1.8 3.4 4.1 4.7 2.2 4.0 4.7 5.3 0.3 1.4 1.9 2.3 0.3 1.3 1.9 2.3
Production Data
DBVDD V 1.8 2.6 3.0 3.3 1.8 2.6 3.0 3.3 1.8 2.6 3.0 3.3 1.8 2.6 3.0 3.3 I (mA) 1.0 1.5 1.7 1.9 0.03 0.053 0.064 0.075 0.2 0.5 1.2 1.9 0.2 0.5 1.2 1.8
UNITS mA
DAC Playback (USB master mode), oscillator and CLKOUT enabled, MCLK=12MHz, fs=48kHz DAC Playback (slave mode using external 12.288 MCLK), fs=48kHz
0
0
mA
A
A
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WM8711BL
HEADPHONE SNR VS AVDD
24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=32Ohm; fs=44.1kHz; Output=-5dBFS (sine)
SNR vs AVDD (DAC Playback to Headphone)
99 98 97 96 95 94 93 92 91 90 1.5 2 2.5 3 3.5 4
AVDD = HPVDD (V)
ANALOGUE SUPPLY CURRENT VS AVDD
24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=16Ohm; fs=44.1kHz; Output=quiescent
SNR (dB)
Supply Current vs AVDD (DAC Playback to Headphone)
4 3.5
IAVDD (mA)
3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4
AVDD = HPVDD (V)
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WM8711BL
MASTER CLOCK TIMING
tXTIL MCLK tXTIH tXTIY
Production Data
Figure 1 System Clock Timing Requirements Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs CLKDIV2=0 unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle tXTIH tXTIL tXTIY 18 18 54 40:60 60:40 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode Test Conditions AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER DACLRC propagation delay from BCLK falling edge DACDAT setup time to BCLCK rising edge DACDAT hold time from BCLK rising edge SYMBOL tDL tDST tDHT TEST CONDITIONS MIN 0 10 10 TYP MAX 10 UNIT ns ns ns
Audio Data Input Timing Information
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WM8711BL
DIGITAL AUDIO INTERFACE - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, slave mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low DACLRC set-up time to BCLK rising edge DACLRC hold time from BCLK rising edge DACDAT set-up time to BCLK rising edge DACDAT hold time from BCLK rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 50 20 20 10 10 10 10 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
MPU INTERFACE TIMING
tCSL CSB tSCY tSCH SCLK tSCL tSCS
tCSH
tCSS
SDIN tDSU tDHO
LSB
Figure 4 Program Register Input Timing - 3-Wire MPU interface Timing
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WM8711BL
Production Data
Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS TEST CONDITIONS MIN 60 80 20 20 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Program Register Input Information
t3 SDIN t6 SCLK t1 t10 t7 t2
t5 t4
t3
t8
Figure 5 Program Register Input Timing - 2-Wire MPU Interface Timing Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SCLK Frequency SCLK Low Pulsewidth SCLK High Pulsewidth Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time t1 t2 t3 t4 t5 t6 t7 t8 t10 600 900 SYMBOL TEST CONDITIONS MIN 0 1.3 600 600 600 100 300 300 TYP MAX 526 UNIT kHz us ns ns ns ns ns ns ns ns
Program Register Input Information
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WM8711BL
DEVICE DESCRIPTION
INTRODUCTION
The WM8711BL is a low power audio DAC designed specifically for portable audio products. Its features, performance and low power consumption make it ideal for portable MP3, CD and mini-disc players. The WM8711BL includes line and headphone outputs from the on-board DAC, configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. The DAC outputs and Line Inputs (BYPASS) are available both at line level and through a headphone amplifier capable of efficiently driving low impedance headphones. The headphone output volume is adjustable in the analogue domain over a range of +6dB to -73dB and can be muted. The design of the WM8711BL minimises power consumption without compromising performance. It includes the ability to power off selective parts of the circuitry under software control, thus conserving power. Separate power save modes can be configured under software control including a standby and power off mode. Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off, volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes may be used dynamically under software control, whenever playback is not required. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. The WM8711BL has two schemes to support the programmable sample rates: Normal industry standard 256/384fs sampling mode may be used. A special USB mode is included, where all audio sampling rates can be generated from a 12.00MHz USB clock. The digital filters used for playback are optimised for each sampling rate used. The digital audio interface can support a range of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The software control uses either a 2 or 3-wire MPU interface.
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WM8711BL
AUDIO SIGNAL PATH
DAC FILTERS
Production Data
The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 6 illustrates the DAC digital filter path.
FROM DIGITAL AUDIO INTERFACE
DIGITAL DE_EMPHASIS
MUTE
DIGITAL INTERPOLATION FILTER
TO LINE OUTPUTS
DEEMP
DACMU
Figure 6 DAC Filter Schematic The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 2. The DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs. REGISTER ADDRESS 0000101 Digital Audio Path Control 2:1 BIT LABEL DEEMP[1:0] 00 DEFAULT DESCRIPTION De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable 3 DACMU 1 DAC Soft Mute Control (Digital) 1 = Enable soft mute 0 = Disable soft mute Note 1 Table 2 DAC Software Control Note 1: 1. Not valid when SR[3:0] = 1111 or 0111. 2. To ensure correct DACMU operation at fs = 88.2kHz, set SR[3:0] = 1000. 3. To ensure correct DACMU operation at fs = 96kHz, set SR[3:0] = 0000.
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Production Data DAC
WM8711BL
The WM8711BL employs a multi-bit sigma delta oversampling digital to analogue converter. The scheme for the converter is illustrated in Figure 7.
FROM DAC DIGITAL FILTERS
TO LINE OUTPUT
Figure 7 Multi-Bit Oversampling Sigma Delta Schematic The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality analogue audio.
LINE OUTPUTS
The WM8711BL provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for driving typical line loads of impedance 10K and capacitance 50pF. The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks directly with AVDD. The scheme is shown in Figure 8. The line output includes a low order audio low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further external filtering is required in most applications.
BYPASS FROM LINE INPUTS
DACSEL
FROM DAC LINEOUT VMID TO HEADPHONE AMP
Figure 8 Line Output Schematic The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling the BYPASS path. Refer to the DAC section for more details. Whenever the DAC is muted or the device placed into standby mode the DC voltage is maintained at the line outputs to prevent any audible clicks from being present.
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WM8711BL
The software control for the line outputs is shown in Table 3. REGISTER ADDRESS 0000100 Analogue Audio Path Control BIT 3 LABEL BYPASS DEFAULT 1
Production Data
DESCRIPTION Bypass Switch 1 = Enable Bypass 0 = Disable Bypass DAC Select 1 = Select DAC 0 = Don't select DAC
4
DACSEL
0
Table 3 Output Software Control The recommended external components are shown in Figure 9.
R2 LINEOUT C1 R1 AGND
AGND
Figure 9 Line Outputs Application Drawing Recommended values are C1 = 10F, R1 = 47k, R2 = 100 C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output.
HEADPHONE AMPLIFIER
The WM8711BL has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed specifically for driving 16 or 32 ohm headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function.
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Production Data The scheme of the circuit is shown in Figure 10.
WM8711BL
FROM DAC VIA LINEOUT
HPOUT VMID
Figure 10 Headphone Amplifier Schematic LHPOUT and RHPOUT volumes can be independently adjusted under software control using the LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to -73dB. The headphone outputs can be separately muted by writing codes less than 0110000 to LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN and RZCEN bits of the headphone output control register. Using these controls the volume control values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises any audible clicks and zipper noise as the gain values are changed or the device muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage input of more than approximately 20mV, then the gain will not be updated. This zero cross function is enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low will force a volume update, regardless of the DC level. LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively, the user can lock the two channels together, allowing both to be updated simultaneously, halving the number of serial writes required, provided that the same gain is needed for both channels. This is achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The corresponding effect on updating RLHPBOTH is also achieved.
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WM8711BL
The software control is given in Table 4. REGISTER ADDRESS 0000010 Left Headphone Out BIT 6:0 LABEL LHPVOL[6:0] DEFAULT 1111001 ( 0dB )
Production Data
DESCRIPTION Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE
7
LZCEN
0
Left Channel Zero Cross detect Enable 1 = Enable 0 = Disable
8
LRHPBOTH
0
Left to Right Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE
0000011 Right Headphone Out
6:0
RHPVOL[7:0]
1111001 ( 0dB )
7
RZCEN
0
Right Channel Zero Cross Detect Enable 1 = Enable 0 = Disable
8
RLHPBOTH
0
Right to Left Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[6:0] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load
Table 4 Headphone Output Software Control
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WM8711BL
The recommended external components required to complete the application are shown in Figure 11.
HPOUT C1 R1 AGND
AGND
Figure 11 Headphone Output Application Drawing Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from rising to a level that may damage the headphones.
DEVICE OPERATION
DEVICE RESETTING
The WM8711BL contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS 0001111 Reset Register BIT 8:0 LABEL RESET DEFAULT not reset DESCRIPTION Reset Register Writing 00000000 to register resets device
Table 5 Software Control of Reset When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 21).
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CLOCKING SCHEMES
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In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. To allow WM8711BL to be used in a centrally clocked system, the WM8711BL is capable of either generating this system clock itself or receiving it from an external source as will be discussed. For applications where it is desirable that the WM8711BL is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input and XTO output pins (see CRYSTAL OSCILLATOR section). For applications where a component other than the WM8711BL will generate the reference clock, the external system Master Clock can be applied directly through the XTI/MCLK input pin with no software configuration necessary. Note that in this situation, the oscillator circuit of the WM8711BL can be safely powered down to conserve power (see POWER DOWN section)
CORE CLOCK
The WM8711BL DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 6 below. REGISTER ADDRESS 0001000 Sampling Control BIT 6 LABEL CLKIDIV2 0 DEFAULT DESCRIPTION Core Clock divider select 1 = Core Clock is MCLK divides by 2 0 = Core Clock is MCLK
Table 6 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode.
CRYSTAL OSCILLATOR
The WM8711BL includes a crystal oscillator circuit that allows the audio system's reference clock to be generated on the device. This is available to the rest of the audio system in buffered form on CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application circuit is shown Figure 12.
XTI/MCLK
XTO
Cp
Cp
DGND
DGND
Figure 12 Crystal Oscillator Application Circuit The WM8711BL crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for high quality audio DACs, regardless of the converter architecture. The WM8711BL architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. In applications where there is more than one source for the master clock, it is recommended that the clock is generated by the WM8711BL to minimise such problems.
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CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for driving external loads. There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to Electrical Characteristics. CLKOUT can also be divided by 2 under software control, refer to Table 7. Note that if CLKOUT is not required then the CLKOUT buffer on the WM8711BL can be safely powered down to conserve power (see POWER DOWN section). If the system architect has the choice between using FCLKOUT = FMCLK or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical Characteristics for timing information. REGISTER ADDRESS 0001000 Sampling Control BIT 7 LABEL CLKODIV2 0 DEFAULT DESCRIPTION CLKOUT divider select 1 = CLOCKOUT is Core Clock divided by 2 0 = CLOCKOUT is Core Clock Table 7 Programming CLKOUT CLKOUT is disabled and set low whenever the device is in reset.
DIGITAL AUDIO INTERFACES
WM8711BL may be operated in either one of the 4 offered audio interface modes. These are:
* * * *
Right justified Left justified I2S DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified mode where 32 bit data is not supported. The digital audio interface receives the digital audio data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section
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Production Data There are four digital audio interface formats accommodated by the WM8711BL. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a DACLRC transition.
1/fs
LEFT CHANNEL DACLRC
RIGHT CHANNEL
BCLK
DACDAT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 13 Left Justified Mode I S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC transition.
2
1/fs
LEFT CHANNEL DACLRC
RIGHT CHANNEL
BCLK
1 BCLK
1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DACDAT
1
2
MSB
LSB
MSB
LSB
Figure 14 I2S Mode
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Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC transition, yet MSB is still transmitted first.
1/fs
LEFT CHANNEL DACLRC
RIGHT CHANNEL
BCLK
DACDAT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
Figure 15 Right Justified Mode
LSB
MSB
LSB
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=1)
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Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=0)
In all modes DACLRC must always change on the falling edge of BCLK, refer to Figures 13,14,15 and 16. Operating the digital audio interface in DSP mode allows ease of use for supporting the various sample rates and word lengths. The only requirement is that all data is transferred within the correct number of BCLK cycles to suit the chosen word length. In order for the digital audio interface to offer similar support in the three other modes (Left Justified, I2S and Right Justified), the DACLRC and BCLK frequencies, continuity and mark-space ratios need more careful consideration. In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC transition to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within the DSP to generate LRC and BCLK will not generate the appropriate DACLRC since it will no longer change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per LRC. In these situations DACLRC can be made non 50:50. In Master mode, DACLRC will be output with a 50:50 mark-space ratio with BCLK output at 64fs x Base Frequency (ie 48kHz). The exception is in 96/88.2k mode where BCLK is MCLK and in USB mode where BCLK is always 12MHz. So for example in 12MHz/32k fs mode there are 375 master clocks per LRC period. Therefore the DACLRC output will have a mark space ratio of 187:188. The DAC digital audio interface modes are software configurable as indicated in Table 7. Note that dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended. The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2's complement. The DAC digital filters process data using 24 bits. If the DAC is programmed to receive 16 or 20 bit data, the WM8711BL packs the LSBs with zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs. The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in Table 8. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the correct channel phase difference, except in DSP mode, where LRP controls the positioning of the MSB relative to the rising edge of DACLRC.
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WM8711BL
To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is controlled via the software shown in Table 8. This is especially appropriate for DSP mode. REGISTER ADDRESS 0000111 Digital Audio Interface Format BIT 1:0 LABEL FORMAT[1:0] DEFAULT 10 DESCRIPTION Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 LRP 0 DACLRC phase control (in left, right 2 or I S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select ( in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge 5 LRSWAP 0 DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right 6 MS 0 Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 7 BCLKINV 0 Bit Clock Invert 1 = Invert BCLK 0 = Don't invert BCLK Table 8 Digital Audio Interface Control Note: If right justified 32 bit mode is selected then the WM8711BL defaults to 24 bits.
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MASTER AND SLAVE MODE OPERATION
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The WM8711BL can be configured as either a master or slave mode device. As a master mode device the WM8711BL controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8711BL responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 9. REGISTER ADDRESS 0000111 Digital Audio Interface Format 6 BIT LABEL MS DEFAULT 0 DESCRIPTION Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode
Table 9 Programming Master/Slave Modes As a master mode device the WM8711BL controls the sequencing of data transfer (DACDAT) and output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 18. DACDAT is always an input to the WM8711BL independent of master or slave mode.
BCLK DSP DECODER
WM8711 DACLRC DAC
DACDAT
Figure 18 Master Mode As a slave device the WM8711BL sequences the data transfer (DACDAT) over the digital audio interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 19.
BCLK DSP DECODER
WM8711 DACLRC DAC
DACDAT
Figure 19 Slave Mode Note that the WM8711BL relies on controlled phase relationships between audio interface BCLK, DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section for detailed information.
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AUDIO DATA SAMPLING RATES
The WM8711BL provides for two modes of operation (normal and USB) to generate the required DAC sampling rates. Normal and USB modes are programmed under software control according to the table below. In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the sample rate control register setting. The WM8711BL can support sample rates from 8ks/s up to 96ks/s. In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8711BL can be directly used within such systems. WM8711BL can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits. REGISTER ADDRESS 0001000 Sampling Control BIT 0 LABEL USB/ NORMAL BOSR DEFAULT 0 DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) 1 0 Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs Normal Mode 96/88.2 kHz 0 = 256fs 0 = 128fs 1 = 384fs 1 = 192fs 5:2 SR[3:0] 0000 DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation
Table 10 Sample Rate Control
NORMAL MODE SAMPLE RATES
In normal mode MCLK is set up according to the desired sample rates of the DAC. For DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.
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Production Data The table below should be used to set up the device to work with the various sample rate combinations. Refer to Digital Filter Characteristics section for an explanation of the different filter types. SAMPLING RATE DAC kHz 48 8 32 96 44.1 8 (Note 1) 88.2 MCLK FREQUENCY MHz 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 BOSR 0 (256fs) 1 (384fs) 0 (256fs) 1 (384fs) 0 (256fs) 1 (384fs) 0 (128fs) 1 (192fs) 0 (256fs) 1 (384fs) 0 (256fs) 1 (384fs) 0 (128fs) 1 (192fs) SAMPLE RATE REGISTER SETTINGS SR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 SR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 SR1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 SR0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 2 1 1 2 1 1 1 DIGITAL FILTER TYPE
Table 11 Normal Mode Sample Rate Look-up Table Notes: 1. 2. 8k not exact, actual = 8.018kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711BL digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate required by the DAC. The exact sample rates achieved are defined by the relationships in Table 12 below. TARGET SAMPLING RATE kHz 8 32 44.1 48 88.2 96 ACTUAL SAMPLING RATE BOSR=0 MCLK=12.288 kHz 8
(12.288MHz/256) x 1/6
BOSR=1 MCLK=18.432 kHz 8
(18.432MHz/384) x 1/6
MCLK=11.2896 kHz 8.018
(11.2896MHz/256) x 2/11
MCLK=16.9344 kHz 8.018
(16.9344MHz/384) x 2/11
32
(12.288MHz/256) x 2/3
not available
32
(18.432MHz/384) x 2/3
not available
not available
44.1
11.2896MHz/256
not available
44.1
16.9344MHz /384
48
12.288MHz/256
not available
48
18.432MHz/384
not available
not available
88.2
(11.2896MHz/256) x 2
not available
88.2
(16.9344MHz /384) x 2
96
(12.288MHz/256) x 2
not available
96
(18.432MHz/384) x 2
not available
Table 12 Normal Mode Actual Sample Rates
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WM8711BL
128/192FS NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8711BL is also capable of being clocked from a 128/192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE DAC kHz 48 44.1 MCLK FREQUENCY MHz 6.144 9.216 5.6448 8.4672 BOSR 0 1 0 1 SAMPLE RATE REGISTER SETTINGS SR3 0 0 1 1 SR2 1 1 1 1 SR1 1 1 1 1 SR0 1 1 1 1 2 2 DIGITAL FILTER TYPE
Table 13 128/192fs Normal Mode Sample Rate Look-up Table
512/768FS NORMAL MODE
512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the device otherwise operates as in Table 9 but with MCLK at twice the specified rate.
USB MODE SAMPLE RATES
In USB mode the MCLK input is 12MHz only. SAMPLING RATE DAC kHz 48 44.1 (Note 2) 8 8 (Note 1) 32 96 MCLK FREQUENCY MHz 12.000 12.000 12.000 12.000 12.000 12.000 BOSR 0 1 0 1 0 0 SAMPLE RATE REGISTER SETTINGS SR3 0 1 0 1 0 0 SR2 0 0 0 0 1 1 1 SR1 0 0 0 0 1 1 1 SR0 0 0 1 1 0 1 1 0 1 0 1 0 3 2 DIGITAL FILTER TYPE
12.000 1 1 88.2 (Note 3) Table 14 USB Mode Sample Rate Look-Up Table Notes: 1. 2. 3. 4. 8k not exact, actual = 8.021kHz 44.1k not exact, actual = 44.118kHz 88.1k not exact, actual = 88.235kHz
All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711BL digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250Fs, with BOSR = 1, the base over-sampling rate is defined at 272Fs. This can be used to determine the actual audio sampling rate required by the DAC.
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Production Data The exact sample rates supported for all combinations are defined by the relationships in Table 15 below. TARGET SAMPLING RATE kHz 8 32 44.1 48 88.2 96 8 12MHz/(250 x 48/8) 32 12MHz/(250 x 48/32) not available 48 12MHz/250 not available 96 12MHz/125 Table 15 USB Mode Actual Sample Rates 88.235 12MHz/136 not available 44.117 12MHz/272 not available ACTUAL SAMPLING RATE BOSR=0 ( 250FS) kHz 8.021 12MHz/(272 x 11/2) not available BOSR=1 (272FS) kHz
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface is disabled (tristate with weak 100k pulldown) at power on. Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS 0001001 Active Control 0 BIT LABEL ACTIVE 0 DEFAULT DESCRIPTION Activate Interface 1 = Active 0 = Inactive
Table 16 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin. MODE 0 1 INTERFACE FORMAT 2 wire 3 wire
Table 17 Control Interface Mode Selection
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8711BL can be controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. The 3-wire interface protocol is shown in Figure 20.
CSB SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 20 3-Wire Serial Interface Notes: 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.
2-WIRE SERIAL CONTROL MODE
The WM8711BL supports a 2-wire MPU serial interface. The device operates as a slave device only. The WM8711BL has one of two slave addresses that are selected by setting the state of the CSB pin.
SDIN SCLK START
R ADDR
R/W
ACK
DATA B15-8
ACK
DATA B7-0
ACK
STOP
Figure 21 2-Wire Serial Interface Notes: 1. 2. B[15:9] are Control Address Bits B[8:0] are Control Data Bits CSB STATE 0 1 ADDRESS 0011010 0011011
Table 18 2-Wire MPU Interface Address Selection To control the WM8711BL on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high. This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see Table 18). If the correct address is received and the R/W bit is `0', indicating a write, then the WM8711BL will respond by pulling SDIN low on the next clock pulse (ACK). The WM8711BL is a write only device and will only respond to the R/W bit indicating a write. If the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address.
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Production Data Once the WM8711BL has acknowledged a correct address, the controller will send eight data bits (bits B[15]-B[8]). WM8711BL will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711BL will then acknowledge again by pulling SDIN low. A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. After receiving a complete address and data sequence the WM8711BL returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits.
POWER DOWN MODES
The WM8711BL contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS 0000110 Power Down Control 3 BIT LABEL DACPD DEFAULT 1 DESCRIPTION DAC Power Down 1 = Enable Power Down 0 = Disable Power Down 4 OUTPD 1 Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down 5 OSCPD 0 Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down CLKOUT Power Down 1 = Enable Power Down 0 = Disable Power Down Power Off Device 1 = Device Power Off 0 = Device Power On Table 19 Power Conservation Modes Software Control
6
CLKOUTPD
0
7
POWEROFF
1
The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used.
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WM8711BL
DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops will result unless the following guidelines are followed. In order to prevent pops, the DAC should first be soft-muted (DACMU), the output should then be de-selected from the line and headphone output (DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Pause or Stop modes. During DACPD the digital audio interface is remains active. OUTPD: Powers down the Line and Headphone Outputs. If this is done dynamically then audible pops may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters Record, Pause or Stop modes. The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 20.
POWER OFF
CLKOUTPD
DESCRIPTION
OSCPD OUTPD DACPD
0 0 0
0 1 1
0 0 1
1 1 1
1 1 1
STANDBY, but with Crystal Oscillator OS and CLKOUT available STANDBY, but with Crystal Oscillator OS available, CLKOUT not-available STANDBY, Crystal oscillator and CLKOUT not-available.
Table 20 Standby Mode In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode. The device can be powered off by writing to the POWEROFF bit of the Power Down register. In POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. Refer to Table 21.
POWER OFF
CLKOUTPD
DESCRIPTION
OSCPD DACPD OUTPD
1 1 1
0 1 1
0 0 1
X X X
1 1 1
POWEROFF, but with Crystal Oscillator OS and CLKOUT available POWEROFF, but with Crystal Oscillator OS available, CLKOUT not-available POWEROFF, Crystal oscillator and CLKOUT not-available.
Table 21 Poweroff Mode
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REGISTER MAP
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The complete register map is shown in Table 23. The detailed description can be found in the relevant text of the device description. There are 8 registers with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER B 15 0 0 0 0 0 0 0 0 0 B 14 0 0 0 0 0 0 0 0 0 B 13 0 0 0 0 0 0 0 0 0 B 12 0 0 0 0 0 0 1 1 1 B 11 0 0 1 1 1 1 0 0 1 B 10 1 1 0 0 1 1 0 0 1 B 9 0 1 0 1 0 1 0 1 1 B8
LRHP BOTH RLHP BOTH 0 0 0
B7
B6
B5
B4
B3
B2
B1
B0
R2 (04h) R3 (06h) R4 (08h) R5 (0Ah) R6 (0Ch) R7 (0Eh) R8 (10h) R9 (12h) R15(1Eh)
LZCEN
LHPVOL
RZCEN 0 0 POWER OFF BCLK INV CLK0 DIV2 0 0 0 CLK OUTPD MS CLKI DIV2 0 0 0 0 0 OSCPD
RHPVOL DAC SEL BYPASS 0 OUTPD DAC MU DACPD 0 0 0 0 1
DEEMPH 1 1
0
LR SWAP
LRP
IWL
FORMAT USB/ NORM ACTIVE
0 0
SR 0 0
BOSR 0
RESET DATA
ADDRESS Table 22 Mapping of Program Registers
REGISTER ADDRESS 0000010 Left Headphone Out
BIT 6:0
LABEL LHPVOL [6:0]
DEFAULT 1111001 ( 0dB )
DESCRIPTION Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE
7
LZCEN
0
Left Channel Zero Cross detect Enable 1 = Enable 0 = Disable
8
LRHPBOTH
0
Left to Right Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load
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Production Data REGISTER ADDRESS 0000011 Right Headphone Out BIT 6:0 LABEL RHPVOL [6:0] DEFAULT 1111001 ( 0dB )
WM8711BL
DESCRIPTION Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE 7 RZCEN 0 Right Channel Zero Cross detect Enable 1 = Enable 0 = Disable 8 RLHPBOTH 0 Right to Left Channel Headphone Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[60] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load 0000100 Audio Path Control 3 BYPASS 1 Bypass Switch 1 = Enable Bypass 0 = Disable Bypass 4 DACSEL 0 DAC Select (Analogue) 1 =Select DAC 0 = Don't select DAC 0000101 Digital Audio Path Control 2:1 DEEMP[1:0] 00 De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable 3 DACMU 1 DAC Soft Mute Control (Digital) 1 = Enable soft mute 0 = Disable soft mute See note 1, page 14 0000110 Power Down Control 3 DACPD 1 DAC Power Down 1 = Enable Power Down 0 = Disable Power Down Outputs Power Down 1 = Enable Power Down 0 = Disable Power Down 5 OSCPD 0 Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down 6 CLKOUTPD 0 CLKOUT Power Down 1 = Enable Power Down 0 = Disable Power Down 7 POWEROFF 1 POWEROFF mode 1 = Enable POWEROFF 0 = Disable POWEROFF
4
OUTPD
1
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WM8711BL
REGISTER ADDRESS 0000111 Digital Audio Interface Format BIT 1:0 LABEL FORMAT[1:0] DEFAULT 10
Production Data DESCRIPTION Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 LRP 0 DACLRC phase control (in left, right or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select ( in DSP mode only) 1 = Mode A (MSB is available on 2nd BCLK rising edge after DACLRC rising edge) 0 = Mode B (MSB is available on 1st BCLK rising edge after DACLRC rising edge) 5 LRSWAP 0 DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Bit Clock Invert 1 = Invert BCLK 0 = Don't invert BCLK
6
MS
0
7
BCLKINV
0
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Production Data REGISTER ADDRESS 0001000 Sampling Control BIT 0 LABEL USB/ NORMAL BOSR DEFAULT 0
WM8711BL
DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) 0 Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs 5:2 SR[3:0] 0000 DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Normal Mode 0 = 256fs 1 = 384fs
1
6
CLKIDIV2
0
Core Clock divider select 1 = Core Clock is MCLK divide by 2 0 = Core Clock is MCLK CLKOUT divider select 1 = CLOCKOUT is MCLK divide by 2 0 = CLOCKOUT is MCLK Activate Interface 1 = Active 0 = Inactive
7
CLKODIV2
0
0001001 Active Control 0001111 Reset Register
0
ACTIVE
0
8:0
RESET
not reset
Reset Register Writing 00000000 to register resets device
Table 23 Register Map Description Note: All other bits not explicitly defined in the register table should be set to zero unless specified otherwise.
DIGITAL FILTER CHARACTERISTICS
The DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER Passband Passband Ripple Stopband Stopband Attenuation Passband Passband Ripple Stopband Stopband Attenuation f > 0.5465fs Table 24 Digital Filter Characteristics 0.5465fs -50 dB f > 0.584fs +/- 0.03dB -6dB 0.584fs -50 0 0.5fs +/- 0.03 dB 0.4535fs dB TEST CONDITIONS +/- 0.03dB -6dB MIN 0 0.5fs +/-0.03 dB TYP MAX 0.416fs UNIT
DAC Filter Type 0 (USB mode, 250fs operation)
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
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WM8711BL DAC FILTER RESPONSES
0.04 0 0.03 -20 0.02
Response (dB)
Production Data
Response (dB)
0.01 0 -0.01 -0.02
-40
-60
-80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 22 DAC Digital Filter Frequency Response-Type 0
Figure 23 DAC Digital Filter Ripple-Type 0
0.04 0 0.03 -20 0.02
Response (dB)
Response (dB)
0.01 0 -0.01 -0.02
-40
-60
-80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 24 DAC Digital Filter Frequency Response-Type 1
Figure 25 DAC Digital Filter Ripple-Type 1
0.02 0 0.01 -20 0
Response (dB)
Response (dB)
-0.01 -0.02 -0.03 -0.04
-40
-60
-80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 26 DAC Digital Filter Frequency Response-Type 2
Figure 27 DAC Digital Filter Ripple-Type 2
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Production Data
0
WM8711BL
0.05
-20
0
Response (dB)
-40
Response (dB)
-0.05
-0.1
-60
-0.15 -80
-0.2
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 28 DAC Digital Filter Frequency Response-Type 3
Figure 29 DAC Digital Filter Ripple-Type 3
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WM8711BL DIGITAL DE-EMPHASIS CHARACTERISTICS
0 0.4 0.3 -2 0.2
Production Data
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 -0.4 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000
Figure 30 De-Emphasis Frequency Response (32kHz)
Figure 31 De-Emphasis Error (32kHz)
0
0.4 0.3
-2 0.2
Response (dB)
Response (dB)
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5000 10000 Frequency (Fs) 15000 20000 -0.4 0 5000 10000 Frequency (Fs) 15000 20000
Figure 32 De-Emphasis Frequency Response (44.1kHz)
Figure 33 De-Emphasis Error (44.1kHz)
0
0.4 0.3
-2 0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5000 10000 15000 Frequency (Fs) 20000 -0.4 0 5000 10000 15000 Frequency (Fs) 20000
Figure 34 De-Emphasis Frequency Response (48kHz)
Figure 35 De-Emphasis Error (48kHz)
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Production Data
WM8711BL
RECOMMENDED EXTERNAL COMPONENTS
3.3V 10F +
3.3V
DBVDD
0.1 F
AVDD
0.1F
+ 10F 3.3V
DGND
10 F 1.5V - 3.3V + 0.1F
AGND
DCVDD
5.6k +
HPVDD
0.1F
+
10F
220pF
5.6k
1F
1M
LLINEIN
HPGND
+
VREF 5.6k +
LOUT RLINEIN
+ 1F
100 47k
220pF
5.6k
1F
1M
VREF
WM8711BL
DACLRC DACDAT BCLK
ROUT
1F
100 47k
DAC
+
Audio Serial Data I/F
LHPOUT
220 F 3-wire Interface 3.3V 10k + 47k
2-wire Interface DGND 3-wire or 2-wire MPU Interface
MODE CSB SDIN SCLK
RHPOUT
220F 47k
CLKOUT VMID
100 0.1F + 10 F
XTI/MCLK
XTO
*GND_PADDLE
Cp
Note
X1
Cp
1. Where possible, it is recommended that NPO or COG type capacitors should be used for best performance. 2. *Ground Paddle in centre of QFN package back side. 3. X1 should have a CL of around 12pF and Cp should be around 15pF.
Figure 36 External Components Diagram
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WM8711BL PACKAGE DIMENSIONS - QFN
Production Data
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Production Data
WM8711BL
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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